ECE 3550 Digital Design

Department of Electrical and Computer Engineering

Welcome to the ECE 3550 Homepage! This is your official information source to Digital Design, offered by the Department of Electrical and Computer Engineering. In this course we will primarily be concerned with the design of multi-input, multi-output system controllers which provide the central control signals that orchestrate the collection of hardware devices found in a digital system. Students will gain hands-on experience with contemporary programmable logic devices (FPGAs). Industry standard CAD tools by Xilinx and Mentor Graphics will be used to design, simulate and implement digital circuits. ECE 3550 is a required course for students majoring in computer engineering . Your instructor this fall is Dr. Janos Grantner, a Professor in the Department.

General Information

Starting with Lab 2 students are required to have the hardware and software as follows:

- Nexys2 Board (Spartan 3E FPGA) that is included in the Parts Kit below

- Large Solderless Breadboard
   These boards are being sold through the IEEE Student Branch. If you don't have a board yet you should see Ms. Judy
   Seymour (ECE Main Office, Hours: 8:00am-5:00pm) to place your order. The price for the board this fall is $30, cash only.
   The final deadline for placing an order is 4:00pm on Monday, 9/12/11. As always, you are free to buy it
   through some vendor, instead.

- Miscallaneous Electronic Parts for the Labs and Projects
    The IEEE Student Branch will help in acquiring the Parts Kits (will order the parts and put together the Kits) for those
   students who place an order and prepay in cash. The price for the Parts Kit this fall is $185, cash only.
   Students should see Ms. Judy Seymour (ECE Dept. Office, Hours: 8:00am-5:00pm) if they want to purchase their Kits
   through the IEEE Student Branch. The final deadline for placing an order is 4:00pm on Monday, 9/12/11. However, students
   are free to buy these parts through vendors, instead.

- Current Xilinx Webpack 13.x.
   Students can download this software package from the Xilinx Web site free of charge.

Course Syllabus ABET Syllabus

Course Outline

Lab Schedule

Instructor's Notes

Data Sheets

Design Clinic

Topics for the Midterm Exam

Solutions to the MT Exam Page1 Page2 Page3

Topics for the Final Exam

Finals Week Office Hours: 3:00-4:00pm, on Monday, December 12, 2011

Homework Grader:    Mr. Jason Anyalebechi
                                  email: anyalj@gmail.com
Phone: (616) 206-1349
                                  Hours: Please see the Extended Lab Hours below

Lab TA:                     Mr. Jafar Abukhait
                                  email: jafar.j.abukhait@wmich.edu
                                  Phone: (269) 873-0869
                                  Hours: Please see the Extended Lab Hours below

Homework Assignments and Solutions

Prelabs

Labs                   Lab Teams

Nexys 2   .UCF File

Please find instructions to run Post-Route simulations using Xilinx ISE 12.2 - 10.1 here.

Please find instructions to run Behavioral and Post-Route simulations using Xilinx ISE 12.3 and ModelsSim 6.6d here.

Information for the Lab Final Exam

Open Lab B-214    Extended Lab Hours    (Effective: 09/16/11)

Additional Open Lab Hours

Please note the extra Lab Hours as follows:

11:00 am - 5:00 pm, on Saturday, 10/22/11 (Mr. Sai Guruva Avuthu)
4:00 - 7:00 pm, on Sunday, 10/23/11 (Mr. Jafar Abukhait)

Students should primarily work on homework and project assignments that require the use of the Xilinx and Mentor Graphics tools in the CAE Computer Lab. They should also download the most recent free versions of WebPack from the Xilinx Web site to their own computers.

There are also eight PCs that run the Xilinx and Mentor Graphics tools in the ECE Department Microcomputer Lab (B-214).

In the Lab B-214 students should sign up for a station with the Lab Monitor student on duty PRIOR to doing any work. Students should also sign off when they leave the station.

Projects

Project #1 Page1 Page2 Test data TEAM ASSIGNMENTS Example Control Architecture

Students should be aware of the fact that the Development Boards' pinouts are different from the chips' pinouts. Conversion
charts are given in the Digilent Manual. You need to visit the Digilent Web site for the information.

Tutorial for MG HDL tools Access to it requires your Bronco NetID and password.

VHDL Tutorial

Xilinx Guide to Create Macros
_________________________________________________________________________________________________________________________

Project #2 Pages 1-2 Page #3 (Timing diagrams) Architecture TEAM ASSIGNMENTS

Project #2 Bonus Pages 1-2 Bonus Page #3 (Timing Diagrams) Architecture

Base Project#2 Demo Steps
Bonus Project#2 Demo Steps (in addition to demonstrating the operations assigned to the Base Project)

In order to get their scores posted on the Web students should create an ID for themselves and turn it in to the course instructor. The ID should be made of six alphanumerical characters that don't refer to the student's name and/or official ID number in any direct way.

Assessments

Important links

Xilinx University Support

Comments to: janos.grantner@wmich.edu

Department of Electrical and Computer Engineering,
Western Michigan University
4601 Campus Drive
Kalamazoo, MI 49008-5329
Primary Author: Janos Grantner
Office: A-246 CEAS
Phone: (269) 276-3154

Intellectual property rights apply.