The goal of the Lab Final to evaluate the individual performance of the students in the lab. Each student should have his/her own Nexys 2 Board and a Breadboard with a properly set up 8-bit DIP Switch unit along with a connected '541-compatible buffer chip (as potential input signals), a bar-LED Unit along with a '540-compatible inverting buffer chip (for visualization of potential output signals) as well as two bounce-free switches. It is your responsibility to verify the correct operation of all circuits and your Nexys 2 Board PRIOR TO the Lab Final Exam. You can also do that during the test but you will not be given more time to complete the test. In addition, students should bring along their Parts Kits and the usual accessories for doing lab experiments. If any other parts are also needed to work on the test circuit the Lab TA will furnish them. Sudents should also have a photocopy of the Hirose connector pinouts and the pinouts of the connectors on the FX2 MIB Board, as well as a photocopy of the pin assignments for the switches and LEDs that are mounted on the Nexys 2 Board.

To begin with, students SHOULD NOT HAVE ANY VHDL program files on a flash drive, or any other media (that includes any file on the C: drive). NEITHER should they attemp to download any VHDL code from any Web site. The use of any communications and messaging devices/services are strictly forbidden. Students should not talk to each other in the lab after the start of the test. A failure to comply with these requirements may result in a zero score in the Lab Final. The Lab Final is of maximum 36 pts., i.e., carries the weight of three regular labs.

You can use your Textbook as a guide for VHDL syntax. The test problem will be a comprehensive one that will include VHDL code development, simulations, implementation and demonstration of the correct operation of a circuit. You will be required to draw a schematic diagram of the whole system on the back of the Lab Exam Book, to print out a hard copy of your VHDL code, the resource allocation and pin assignments for the FPGA, as well as behavioral simulation timing diagrams, as directed. You should turn in these documents to the Lab TA. In addition, you should demonstrate the operation of your solution to the assigned problem. The Lab TA CAN'T HELP you in debugging your design this time. The test will take approx. 1 hour and 20 minutes. You cannot leave the lab even if you finish early, the Lab TA will tell you when you can leave (all students will leave at once).

A Sign-up Sheet will be posted on the door of the B-214 Lab (inside). You are to sign up for an open slot (up to six students in a Lab Final Session). A no-show will be given zero credit for the test. Make up tests will only be given under extraordinary circumstances and only if the course instructor, or the Lab TA has been notified prior to the test.