VHDL Basics
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Documentation Standards for Logic Design
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Timing Hazards in Combinational Circuits
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Function
Hazards Page1
Methods to Minimize Combinational
Logic Page1
Fault Detection in Combinational Circuits
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Combinational Logic design with PLDs
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Systems-level Combinational Logic
Design Page1
Files to practice with
WebPack 9.x and ModelSim 6.x
Combinational Logic Design
VHDL file for the
TI'138 decoder
Please visit to the Design Clinc Section for additional code examples
and .do files
Introduction to Sequential Logic
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Analysis of Synchronous Sequential Circuits
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Synthesis of Synchronous
Sequential Circuits
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More Examples on State Reduction
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Self-starting Circuits
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Digital Design with Synchronous State Machines
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Algorithmic State Machine (ASM) Method
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Example: T-Bird Blinker Control
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T-bird VHDL file Simulation (.do)
file
Hints for Project #1
2C Number Representation and Arithmetic Overflow -
refer to the ECE 4510 Notes
Partial Block Diagram for
Project #1
ASM Chart for a Bit Serial Adder Page1
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ASM Chart for a Bit Counter
Impediments to Synchronous Design
Clock Skew Page1
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Asynchronous Inputs Page1
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Synchronizer Failure and Metastability Estimation Page1
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Synchronous Sequential Circuit Design from Word Description
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Asynchronous Sequential Circuit Architecture
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Asynchronous Sequential
Circuit Design
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Asynchronous Sequential Circuit Synthesis Example
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Data Lock Out T FF Design Example Using
VHDL .vhd
File .do File
Critical Race Free State Assignment Examples
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Closure Criteria Examples
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Parallel I/O Chip
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Hints for Project #2
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DFF with Combinational Logic Feedback
Two-Input-Two-Output
Asynchronous Sequential
Circuit Design Example
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Analysis of Asynchronous Sequential
Circuits
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Incompletely Specified Synchronous SLC
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Design of State Machines by Microprogram Sequencers
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Open Collector Logic and
Buffers
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Variable-Entered Maps
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