Review for the Final Exam
10:15am-12:15pm, Wenesday, December 14, 2011 in Room D-206
Please bring your Exam Blue/Green Book to the test. The Final
Exam will
be a comprehensive test but more emphasis will be given to topics
covered after the Midterm Exam. It will be a closed book, no notes test
with the exception of the assigned Textbook for VHDL syntax.
Topics covered in class include:
- Active-H and Active-L logic signals
- Timing diagrams
- Static, dynamic and function hazards in combinational logic
circuits
analysis of combinational logic circuits for potential hazards
design of hazard-free circuits
- Stuck-at faults and bridging faults in combinational logic
circuits
find test vectors to detect faults
- Design and simulation of combinational logic circuits using
VHDL and ModelSim
- State machine design using ASM Charts
- Design and simulation of synchronous sequential logic circuits
using VHDL and ModelSim
- Design of asynchronous sequential logic circuits
Primitive Flow Maps
state reduction (incompletely specified state table)
reduced state table
critical race-free state
assignment
unused states, hang state problem
essential hazards
circuit implementation by
combinational logic with feedback
- Design and simulation of asynchronous sequential logic
circuits using VHDL and ModelSim
- Analysis of asynchronous logic circuits
Is the circuit minimal?
Is the circuit free of static hazards?
Is the state assignment free of critical race?
Does the circuit have essential hazards?
State transition graph
Timing diagrams
- Model of a programmable I/O chip (not a test problem)
- Mode0 and Mode1 I/O with the i82C55A chip
- Analysis of synchronous sequential circuits
Timing diagrams only
- Microprogram sequencers to implement state machines (not a
test problem)
- Open-Collector/Drain logic and buffers