ECE 4500 Digital Electronics

Department of Electrical and Computer Engineering

Welcome to the ECE 4500/5540 Home Page! This is your official information source to Digital Electronics, offered by the Department of Electrical and Computer Engineering. In this course, we will be primarily concerned with fundamental device models, and techniques for analyzing and designing digital integrated circuits. ECE 4500 is a required course for undergaduate students majoring in computer engineering. ECE 5540 is one of the elective fundations courses for graduate students enrolled either in the Computer Engineering or Electrical Engineering Master's Program. Your instructor this fall semester is Dr. Janos Grantner, a Professor in the Department. 

General Information

Course Syllabus                     ABET Syllabus    

Course Outline

Lab Schedule 

Lab Outline

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LAB TEAM ASSIGNMENTS
            
6:30-9:20pm, Thursday, B-214             ECE 4500 Teams        ECE 5540 Teams

A link to the Mentor Graphics Tutorials developed by Ramakrishna Gottipati and revised by Sai Guruva Avuthu is given here. Please note that the Linux-based, most recent version of the software may have a somewhat different GUI.

Instructions to print from the Suns without a black background. It may need to be revised for the Linux PCs.

Prelab Assignments

Lab Assignments

Extended Lab Hours in B-214 (effective: 09/19/11)

Additional Open Lab Hours

Please note the extra Lab Hours as follows:

11:00 am - 5:00 pm, on Saturday, 10/22/11 (Mr. Sai Guruva Avuthu)
4:00 - 7:00pm, on Sunday, 10/23/11 (Mr. Jafar Abukhait)

11:00 am - 5:00 pm, on Saturday, 10/29/11 (Mr. Yousef Atoum)
4:00 - 7:00 pm, on Sunday, 10/30/11 (Mr. Jafar Abukhait)

A link to the Tutorial on remote access to the Mentor Graphics tools on a Linux machine
It has been developed by Matthew Terry.

A link to the Tutorial on remote access to Xelga
It has been developed by Dustin Spicuzza.

Lab TA: Mr. Sai Guruva Avuthu

Hours: please see the Extended Lab Hours above
Email:  saiguruva.r.avuthu@wmich.edu
Phone: (269) 779-8030                        

Grader Assistant: Mr. Yousef Atoum

Hours: please see the Extended Lab Hours above
Email: yousef.a.atoum@wmich.edu
Phone: (269) 276-6791

Notes

Problem Solving and Design Clinic

How to Use Your Mentor Graphics Account - A Message from Your Lab TA

Homework Assignments and Solutions
The new due date for Homework #6 is 11/09/11!

Assessments

Information for the Lab Final
 Midterm Exam Review (10/14/11, in C-124)    Page1    Page2     Page3    Page4    Page5 
Students should bring along their Blue/Green Exam Books and calculators to take the test. The exam will be of a closed books, no notes test. The  basic formulas needed to solve the problems will be provided on a Supplement Sheet.


Midterm Exam Solutions     Page1     Page2     Page3     Page4 
    

Projects

ECE 4500 and ECE 5540
          ECE 5540 Project#1 Teams

Demo Times :    

In your Project Report you are required to provide for individual transistor-level schematic diagrams, transistor-level
layouts and LVS Check Reports (ICStation) for all layouts.
You are also required to run Calibre but only on the full project layout. You should include in your report printouts
of the DRC Check results file, the LVS check file (the cell-level LVS should pass), the source netlist, the layout netlist,
and the top page of the Parasitic Extraction Report.

Please note that the VDD and VSS pins of your symbols should be named as VDD_local and VSS_local, or any name
other than VDD and VSS, respectively, for Calibre to work. If you have missed to do that then just go to Symbol,
Edit-> Text and rename them. Then in the schematics, right click on the symbol and select Auto -> Update. Ignore
in the Check and Save if it complains about VDD_local, and VSS_local.

Make sure that your symbol names do not start with XOR, AND, NAND, etc., because the simulator will recognize them
as some default name and will fail.

Please note that if any work is done on the project after 3:00pm (that includes printing and assembling the Project
Report) then the project will be considered late by one day (the penalty is the loss of 10% of credit).

ECE 5540

Project #2

ECE 5540 Project #2 Teams

Demo Times :    

ECE 4500 Project #2 and ECE 5540 Project #3

   Demo Times :   

Design hints for Project #2/#3 are given under the Design Clinic Section.

With respect to the definition of the Read access time, Read cycle time, Write access time and Write cycle time,
respectively, please refer to Fig. 12-1 of the Text (on Page 625). Since access to either bank of registers is
initiated by the asserted Bank Select signal please use that as your time reference.

In your Project Report you are required to provide for individual transistor-level schematic diagrams, transistor-level
layouts and LVS Check Reports (ICStation) for all layouts.
You are also required to run Calibre but only on the full project layout. You should include in your report printouts
of the DRC Check results file, the LVS check file (the cell-level LVS should pass), the source netlist, the layout netlist,
and the top page of the Parasitic Extraction Report.

Please note that the VDD and VSS pins of your symbols should be named as VDD_local and VSS_local, or any name
other than VDD and VSS, respectively, for Calibre to work. If you have missed to do that then just go to Symbol,
Edit-> Text and rename them. Then in the schematics, right click on the symbol and select Auto -> Update. Ignore
in the Check and Save if it complains about VDD_local, and VSS_local.

Make sure that your symbol names do not start with XOR, AND, NAND, etc., because the simulator will recognize them
as some default name and will fail.

          Guidelines for Project #2/#3 and Project #2/#3 Bonus demonstrations

Please note that if any work is done on the project after it is due (that includes printing and assembling the Project
Report) then the project will be considered late by one day (the penalty is the loss of 10% of credit).

Finals Week Office Hours:  5:30-6:30pm, on Friday, December 9, 2011   

Final Exam Review

Students should bring along their Blue/Green Exam Books and calculators to take the test. The exam will be of a closed
books, no notes test. The  formulas necessary to solve the problems will be provided on a Supplement Sheet.
For the complete list of topics please ALSO read the  Review Pages posted for the Midterm Exam above.
WMU Help
Comments to: janos.grantner@wmich.edu

Department of Electrical and Computer Engineering,
Western Michigan University,
Room A-246, CEAS
Kalamazoo, MI 49008-5329
Phone: (269) 276-3154

Primary Author: Janos Grantner  
Intellectual property rights apply.