• Designing Combinational Logic Gates (Ch. 6)

                  - Dynamic CMOS Design (6.3)
                           - Basic architecture
                           - Speed and power dissipation
                           - Signal integrity issues
                           - Cascading dynamic gates
                                  - Domino Logic
                                  - np-CMOS Logic

• Designing Sequential Logic Circuits (Ch. 7)

                 - Timing metrics
                 - Classification of memory elements
                 - Static Latches and Registers  (7.2)
                            - MUX-based and overpowered feedback loop
                            - Master-Slave
                            - Static SR FFs
                 - Dynamic Latches and Registers  (7.3)
                            - Transmission gate edge-triggered
                            - C2MOS
                            - TSPCR
                 - Alternative Register Styles  (7.4)
                 - Pipelining (7.5)
                            -  NORA-CMOS
                 - Non-Bistable Sequential Circuits
                            - Schmitt trigger
                            - One-shot
                            - Astable

• Designing Memory and Array Structures (Ch. 12)

                - Memory classification
                - Memory architectures and building blocks
                - The memory core (12.2)
                            - ROM cells (12.2.1)
                            - Read-Write memories (RAM) (12.2.3)
                                    - SRAM
                                    - DRAM (3T, 1T)
                           - CAM
                - Memory peripheral circuitry (12.3)
                           - Address decoders
                           - Sense amplifiers
                           - Drivers and buffers
                           - Timing and control

• Timing Issues in Digital Circuits (Ch. 10)

                - Timing classification of digital systems (10.2)
                - Synchronous design (10.3)
                          - Clock skew
                          - Clock jitter
                        
                - Self-timed circuit design (10.4)
                         - Completion signal generation (10.4.2)
                         - Self-timed signaling (10.4.3)
                                - Muller C-element

• The Wire (Ch 4)

                          - Capacitance
                          - Resistance
                          - Inductance
                          - Electrical wire models
                          - Transmission line model