ECE 5570 Design of Reconfigurable Digital Machines
Department of Electrical and Computer Engineering
Welcome to the ECE 5570 Homepage! This is your official information
source
to Design of Reconfigurable Digital Machines, offered by the
Department of Electrical and
Computer
Engineering. In this course we will primarily be concerned with the
design
of complex combinational and sequential logic circuits and of
system-on-chip architectures. Students will gain hands-on experience
with
contemporary programmable logic devices (FPGAs). Industry
standard CAD tools by Xilinx and Mentor Graphics will be used to
design, simulate and implement digital circuits. ECE 5570 is one of the
foundation courses for graduate students
majoring
in
computer engineering . Your instructor this fall is Dr.
Janos
Grantner, a Professor in the Department.
Please find instructions below on how to run post-route simulations
(below "Projects").
General Information
Starting
with Week 2
students are required to have the software as follows:
- Xilinx
Webpack 12.2 along with the most recent ModelSim MXE III Starter
Edition by Mentor
Graphics
Students can download these software packages from the
Xilinx Web site free of charge.
Starting
with Week 3
students are required to have the hardware as follows:
- Nexys 2 Board (Spartan 3E FPGA) that is
included in the Parts Kit below
- Large
Solderless Breadboard
These boards
are being sold
through the IEEE Student Branch. If you don't have a board yet
you should see Ms.
Mariann
Cardenas (ECE Main Office, Hours: 8:00am-5:00pm)
to place your order. The
price will be about $30, cash only.
The final
deadline for placing an order is 4:00pm on Monday,
09/13/10. As
always, you are free to buy it through some vendor,
instead.
-
Miscellaneous Electronic Parts for
Projects
The IEEE Student Branch will help in acquiring
the Parts Kits
(will order the parts
and put together the Kits) for
those
students who place an order and prepay in cash. The
price for the Parts Kit this fall is $180, cash
only.
Students
should see Ms. Mariann Cardenas (ECE Dept. Office, Hours: 8:00am-5:00pm) if
they want to purchase their Kits
through the IEEE
Student Branch. The final
deadline for placing an order is 4:00pm on Monday, 09/13/10. However,
students
are
free to buy these parts through vendors, instead.
Course Syllabus
ABET
Syllabus
Topics for the Final
Exam
Finals Week Office Hours:
4:30-5:30pm, on Friday, 12/10/10
Open Lab
B-214
Extended Lab Hours (Effective: 10/04/10)
Students should primarily work on homework
and project assignments
that require the use of the Xilinx and Mentor Graphics tools in the CAE
Computer Lab. They should also download
the most recent free versions of WebPack and ModelSim MXE III Starter
Edition from the
Xilinx Web site to their own computers.
There are also eight PCs that run the Xilinx and
Mentor
Graphics tools in the ECE Department Microcomputer Lab (B-214).
In
the Lab B-214 students should sign up for a station with the
Lab
Monitor
student on duty PRIOR to doing any work. Students should also sign off when they leave the station.
Projects
Project #1
Page2 Page3
Test data
TEAM
ASSIGNMENTS
Nexys 2 .UCF File
Please find instructions to run
Post-Route
simulations using Xilinx
ISE 12.2 - 10.1 here.
Students should be
aware of the
fact that the Development Boards' pinouts are different from the chips'
pinouts. Conversion
charts are given in the Digilent Manual. You need to visit the
Digilent Web site for the
information.
Please visit to the ECE3550 Web Page to access to the Tutorial for MG
HDL
tools.
Access requires
your Bronco NetID and password.
_________________________________________________________________________________________________________________________
Project #2 Page1 Page2 Page3 Symbolic Testprogram
TEAM
ASSIGNMENTS
Project #3 Page1 Page2 Page3
TEAM
ASSIGNMENTS
In order to get their scores posted on the Web
students should create an ID for themselves and
turn it in to the course instructor.
The ID should be made of six alphanumerical characters
that
don't refer to the student's name and/or official ID number in
any
direct way.
Information for the Final Exam
Review
Students should bring along their Blue Exam Books
to take the test. The exam will be of a closed books,
no notes test. However, students will be allowed to use their own
hardcopy of the VHDL Tutorial that is accessible through the ECE 3550
Class Home Page.
Assessments
Important links
Xilinx
University Support
Comments to: janos.grantner@wmich.edu
Department of Electrical and Computer Engineering,
Western Michigan University
4601 Campus Drive
Kalamazoo, MI 49008-5329
Primary Author: Janos Grantner
Office: A-246 CEAS
Phone: (269) 276-3154
Intellectual property rights apply.