• Review of Timing Hazards in Combinational Logic Circuits
  

• Review of the Key Concepts for Designing Synchronous State Machines
  

                 - Synchronization criteria
                 - ASM Chart
                 - No hang states       

• VHDL Code for

                - Combinational logic (behavioral and structural, use of libraries)
                - Synchronous state machines (state encoding, reset, combinational logic process, clock process)
                - Designing simulation stimuli (test bench, macro commands)
                - TS buses
                - Modular blocks
                - Parameterized design
                - Dedicated multipliers
                - LUT-based SRAM, Block SRAM

• CPLD and FPGA Architectures                   

• Introduction to Reconfigurable Computing

• Platform FPGAs

• Design and Implementation
  

           - Placement and routing
         - Static and dynamic reconfiguration

• Reconfiguration - Partitioning

                 - Spatial
                 - Temporal

• Partial reconfiguration

• Application Examples