Extension Principle
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Crisp Relations
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VHDL design files and simulation script files

Xilinx WebPack and MG ModelSim  files

Combinational Logic Design

VHDL file for TI 74138 Decoder    Simulation file      

VHDL file for 1-of-4 MUX             Simulation file      

VHDL files for AS885     code1      code2      Simulation file    

Sequential Logic Design

T-Bird VHDL file         Simulation file

Arbiter code                 Simulation file

Asynchronous DRAM Controller code

Bidirectional Three-State Buffer code           Data Register code
When you need to simulate a bidirectional, TS bus you have to design/schedule carefully when you want
to enforce/remove a simulated data item on/from the bus. Please refer to the examples at the end of the
Mentor Tutorials in the ECE 3550 Web Page. In the .do file, a force .... -cancel @0ns, or unforce.....@...ns command will turn off a permanent drive of the bus by ModelSim. The schedule of your forced stimuli should be carefully synchronized
with the control of your TS buffers that conditionally drive the same bus lines.

Hierarchical VHDL Design Example
VHDL code

For VHDL Tutorials and other useful information please visit to the ECE 3550 Web Page, or the Xilinx Web Page, or search the Web.

For Xilinx FPGA Data Sheets and ML505 information please visit to the Xilinx Web site at www.xilinx.com.

Link to the Vertex-5 Board

Link to the Vertex-5 chip



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TSK (Takagi - Sugeno - Kang) Model

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