Lecture Topic Smoke Trail

September

5 On Tuesday, we finished our discussion of Boolean Algebra, covering the topics of Boolean functions and characterization by truth tables. We also demonstrated how to reduce Boolean functions to most simple forms by applying the Boolean theorems and postulates. Finally we discussed the significance of minterms for generating Boolean functions from truth tables.

7 On Thursday we began discussions of the subject of Logic Gates and Circuits. In particular, we demonstrated how logic gates have been designed to realize useful Boolean functions.

12 On Tuesday, we discussed the concept of equivalent symbols for NAND and NOR gates, taken from the lecture topic Logic Gates and Circuits. These equivalent symbols proved to be very useful when constructing standard-form circuits, which was the next subject we discussed. In particular, a NAND-NAND circuit was shown to yield the same functionality as the AND-OR circuit. The NOR-NOR was also shown to be equivalent to the OR-AND. We ended our lecture by dicussing Digital Logic families.

14 On Thursday, we examined some MOS circuitry for NAND NOR and NOT circuits. We also began discussions of The Binary Number System by introducing the concept of binary addition. We also showed some circuitry that could be used to add binary numbers.

19 On Tuesday, we showed examples of number base conversion between base 10 and other common number bases (2, 8, and 16). 2^k conversions, that is between binary (base 2) and octal (base 8) as well as hexadecimal (base 16) were also illustrated. We ended the lecture by discussing the 2's complement method of subtracting binary numbers.

21 On Thursday, we covered the subject of Minterms and Maxterms. In particular, we showed how to generate minterm list forms and maxterm list forms from a truth table. We also looked at a comparison of minterms verses maxterms, to obtain extra insight into these matters.

26 On Tuesday, we demonstrated the CAD package PLDSHELL. which will be used in the lab this week. After this, we introduced the concept of K-maps as an extension of a Venn diagram.

28 Thursday was spent discussing K-maps and going over some concepts for the first exam. We learned how to plot a K-map from a truth table, as well as read a SOP expression from it. We also examined how to handle don't cares, as well as how to read POS expressions from a K-map as well.

October

3 Exam I

5 Review of Exam I

10 On Tuesday, we began discussions of Important Combinational Logic Circuits, introducing the 3 to 8 decoder and 8 to 1 multiplexer circuits. In particular, we showed how to use the decoder as a SOP function generator.

12 Thursday was spent looking at the encoder (briefly) and the demultiplexer. In particular, we showed how to implement a 1 to 8 DeMUX from a 3 to 8 Decoder. We also began discussions of the read-only memory, and we illustated a block diagram model of a ROM using decoder and encoder elements.

17 On Tuesday we showed how a ROM is implemented from a decoder transistor array and a encoder transistor array. We also discussed the programmable logic device as an extention of a ROM.

19 On Thursday, we began discussions of Sequential Logic Circuits, and illustrated the difference between these circuits and combinational logic circuits. We also introduced the latch circuit, which is the simplest kind of SLC.

24 Tuesday was spent discussing the subject of Flip-Flops and Clocks . We demonstrated some simple clock frequency calculations, as well as introduced the SR flip-flop.

26 Thursday was spent discussing the D flip-flop as well as the JK flip-flop

31 We began discussions of the subject of Synchronous SLC Analysis and Design, introducing the concept of a state diagram and state table.

November

2 We applied the five step sequential logic circuit (SLC) design procedure to the two SLC design problems found in Task One and Task Two-Page1 and Task Two-Page2 of Lab Nine, as discussed in the course packet.

7 We introduced the concept of code sequence detection, and formulated a state diagram for a four bit code detector, with no overlap. We then considered how to design state diagrams for code sequence detectors having nonzero bits of overlap.

9 We applied the five step sequential logic circuit (SLC) design procedure to iterate two designs for a 0101 code sequence detector. State assignments were given for the first design, and then enhanced to produce a more optimal second design. We also demonstrated how to enter this SLC design into a PLD, and simulate the results.

14 On Tuesday, we began discussions of the subject of Important Types of Sequential Logic Circuits, and covered shift registers. We also discussed the design of a bidirectional shift register, such as found in Task Two of Lab Ten.

16 Thursday was spent discussing synchronous counters and ripple counters. We compared their state diagrams, and identified the ripple effect.

21 Exam II. No labs this week, except Monday's lab, which meets this week to get caught up with the other sections.

23 Thanksgiving

28 Review of Exam II

30 We looked over the survey results (to the tune of the Nutcracker...). We then began discussions of the subject of A Simple Computer. We showed a block diagram of the Mark III serial computer, constructed from the ICs used in the ECE 250 laboratory. We also reviewed the Mark III instruction set.

December

5 On Tuesday, we went over the Mark III computer state diagram, and considered the design of a sample program, with which we added two numbers.

7 On Thursday, we examined the hardware design of the Mark III computer.

11--Monday! Final Exam.