This exercise will examine the properties and applications of some
important combinational logic circuits. Circuits to be considered include
the decoder, multiplexer, encoder, demultiplexer as well as the ROM (read
only memory).
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An 8line to 1line multiplexer is connected as shown, where output
Y = F(x,y,z) and z is the least significant input. Which of the following
functions does Y generate?
 F(x,y,z) = z
 F(x,y,z) = y
 F(x,y,z) = z'
 F(x,y,z) = x
 F(x,y,z) = x + y'

Which of the following is the correct output expression for an eight to
one MUX?
 Y = D(m0 + m1 + m2 +...+ m7)
 Y = (D0*m0 + D1*m1 + D2*m2 +...+ D7*m7)*E
 Y = m0' + m1' + m2' +...+ m7'
 Y = (D0*m0' + D1*m1' + D2*m2' +...+ D7*m7')*E
 Y = D*m0 + D*m1 + D*m2 +...+ D*m7

A 3line to 8line decoder is connected as shown. Where x, y and z are
inputs (z is the least significant input digit) and F is an output.
Which of the following expressions correctly describes F?
 F(x,y,z) = z
 F(x,y,z) = x
 F(x,y,z) = z'
 F(x,y,z) = yz
 F(x,y,z) = x'

A circuit which gates one input of data line to one of 2^n output lines is
defined as a
 MUX
 DeMUX
 Encoder
 Decoder
 ROM

A 3line to 8line decoder is connected as shown, where x, y, and z are
inputs (z is the least significant input digit) and F is an output.
F = 1 when
 All 3 inputs are logical 0
 2 out of 3 inputs are logical 0
 1 out of 3 inputs are logical 0
 No input is logical 0
 None of the above

A circuit which translates n input lines into an mbit code word, where
n <= 2^m is defined as a
 MUX
 DeMUX
 Encoder
 Decoder
 ROM

Which of the following correctly describes output Yi (i: 0 to 7)
of the 3line to 8line decoder, where mi is the ith minterm of the
CBA select lines and E is the enable input?
 Yi = mi*E
 Yi = (mi*E)'
 Yi = (mi*E')'
 Yi = (mi'*E)'
 Yi = (mi'*E')'

Which of the following occurs when the enable input to a 3line to 8
line decoder goes low (i.e. E=0)?
Assume outputs of the decoder are activelow.
 All outputs go low(0)
 All outputs go high(1)
 The outputs go to a random pattern of 0's and 1's
 Power to the decoder chip is lost
 None of the above

A ROM having 9 address lines and 16 outputs is given. What is the total
capacity = C? Note: K = 1024 = 2^10
 25K
 13K
 8K
 9K
 10K

A ROM having a total capacity of 64K bits (K = 1024 = 2^10) is given. If
the ROM is known to have 8 outputs, how many address lines are there?
 11
 12
 13
 14
 15

ReadOnly Memories (ROM's) are constructed from which of the
following components? Select the best answer.
 A DECODER and a MUX
 A MUX and a DEMUX
 A DECODER and an ENCODER
 A MUX and an ENCODER
 An ENCODER and a DEMUX

Which of the following best describes how to construct a 1line to 8line demultiplexer from a 3line to 8line decoder:
 Connect the decoder input select lines CBA to D.
 Connect the decoder enable input to D.
 Connect the decoder input data lines to Di.
 Connect the ith decoder output to Di.
 Connect Y to D and W to D'.
