This quiz covers PLDs (programmable logic circuits) and the basics of SLCs
(sequential logic circuits), including latches. Please refer to the lecture notes for background material covering this subject..
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Given the partial NMOS ROM decoder shown, having address inputs A2,
A1, and A0 (A0 is LSB), identify the decoder output (select line) Y.
 Y = Y0
 Y = Y2
 Y = Y3
 Y = Y4
 Y = Y5

Given the partial NMOS EPROM encoder shown, where Y is some select line,
determine the values of the output data lines D2D1D0 when Y = 1.
 D2=0 D1=0 D0=0
 D2=1 D1=0 D0=1
 D2=1 D1=1 D0=0
 D2=0 D1=1 D0=0
 D2=0 D1=0 D0=1

Indicate the dots required to be connected (1 to 8) to implement a NOR
function using the PLD AND array shown below:
 Dots at 3, 8
 Dots at 2, 4, 7, 8
 Dots at 2, 4 (only)
 Dots at 5, 7, 1, 2
 Dots at 5, 7 (only)

In general, the NEXT STATE of a sequential logic circuit is determined
by the
 MEMORY ELEMENTS
 INPUT LOGIC BLOCK
 OUTPUT LOGIC BLOCK
 INPUTS only
 OUTPUTS only

If a sequential circuit possesses N memory elements (binary cells or
flip flops), what is the maximum number of states could it have?
 N
 N^2
 2N
 2^N
 None of these

Which of the following statements concerning the basic latch circuit is
FALSE?
 A latch circuit may be constructed with NOR Gates.
 A latch is a synchronous sequential logic circuit.
 The Q and Q' outputs of a latch can, under certain input conditions, be
equal.
 The latch is utilized in all flipflop circuits.
 Allowable modes of operations of the latch include the SET, RESET and
NO CHANGE modes.

Which of the following modifications to the sequential logic circuit
(SLC) block diagram would most likely lead to nonsequential behavior?
 INPUT lines are disconnected, but the CLOCK line is not affected.
 The INPUT LOGIC BLOCK is removed so that the MEMORY ELEMENTS
inputs and outputs are interfaced directly.
 The OUTPUT LOGIC BLOCK is removed so that the MEMORY ELEMENTS
outputs are directly connected to the SLC OUTPUTLINES.
 The feedback path between the MEMORY ELEMENTS and the INPUT LOGIC
BLOCK is opened.
 No modification stated above would lead to nonsequential behavior.

In general, the PRESENT STATE of a sequential logic circuit is
determined by the
 MEMORY ELEMENTS
 INPUT LOGIC BLOCK
 OUTPUT LOGIC BLOCK
 INPUTS only
 OUTPUTS only
