Copyright © Dean Johnson 2009 (johnson@wmich.edu)

Quiz#7: PLDs and SLCs

This quiz covers PLDs (programmable logic circuits) and the basics of SLCs (sequential logic circuits), including latches. Please refer to the lecture notes for background material covering this subject.. (Go back to homepage.)


  1. Given the partial NMOS ROM decoder shown, having address inputs A2, A1, and A0 (A0 is LSB), identify the decoder output (select line) Y.

    1. Y = Y0
    2. Y = Y2
    3. Y = Y3
    4. Y = Y4
    5. Y = Y5

  2. Given the partial NMOS EPROM encoder shown, where Y is some select line, determine the values of the output data lines D2D1D0 when Y = 1.

    1. D2=0 D1=0 D0=0
    2. D2=1 D1=0 D0=1
    3. D2=1 D1=1 D0=0
    4. D2=0 D1=1 D0=0
    5. D2=0 D1=0 D0=1

  3. Indicate the dots required to be connected (1 to 8) to implement a NOR function using the PLD AND array shown below:

    1. Dots at 3, 8
    2. Dots at 2, 4, 7, 8
    3. Dots at 2, 4 (only)
    4. Dots at 5, 7, 1, 2
    5. Dots at 5, 7 (only)

  4. In general, the NEXT STATE of a sequential logic circuit is determined by the

    1. MEMORY ELEMENTS
    2. INPUT LOGIC BLOCK
    3. OUTPUT LOGIC BLOCK
    4. INPUTS only
    5. OUTPUTS only

  5. If a sequential circuit possesses N memory elements (binary cells or flip flops), what is the maximum number of states could it have?

    1. N
    2. N^2
    3. 2N
    4. 2^N
    5. None of these

  6. Which of the following statements concerning the basic latch circuit is FALSE?

    1. A latch circuit may be constructed with NOR Gates.
    2. A latch is a synchronous sequential logic circuit.
    3. The Q and Q' outputs of a latch can, under certain input conditions, be equal.
    4. The latch is utilized in all flip-flop circuits.
    5. Allowable modes of operations of the latch include the SET, RESET and NO CHANGE modes.

  7. Which of the following modifications to the sequential logic circuit (SLC) block diagram would most likely lead to non-sequential behavior?

    1. INPUT lines are disconnected, but the CLOCK line is not affected.
    2. The INPUT LOGIC BLOCK is removed so that the MEMORY ELEMENTS inputs and outputs are interfaced directly.
    3. The OUTPUT LOGIC BLOCK is removed so that the MEMORY ELEMENTS outputs are directly connected to the SLC OUTPUTLINES.
    4. The feedback path between the MEMORY ELEMENTS and the INPUT LOGIC BLOCK is opened.
    5. No modification stated above would lead to nonsequential behavior.

  8. In general, the PRESENT STATE of a sequential logic circuit is determined by the

    1. MEMORY ELEMENTS
    2. INPUT LOGIC BLOCK
    3. OUTPUT LOGIC BLOCK
    4. INPUTS only
    5. OUTPUTS only